Video processing system

ABSTRACT

In a video processing system which divides HD-size image data into a plurality pieces of sub-image data and performs image processing for upconversion to 4K×2K image data, four image processors synchronous with an HD signal each process a corresponding one of the four pieces of sub-image data. In this case, the image processors process the four pieces of sub-image regions while causing the four pieces of sub-image regions to overlap at their division boundaries, and particularly process the overlapping regions during respective blanking periods. After the image processing of the image processors, the overlapping data is removed. Thereafter, the pieces of image data of the four sub-regions are combined. Therefore, the division boundaries of the pieces of sub-images can be processed without a degradation in image quality.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of PCT International ApplicationPCT/JP2009/002257 filed on May 21, 2009, which claims priority toJapanese Patent Application No. 2008−147900 filed on Jun. 5, 2008. Thedisclosures of these applications including the specifications, thedrawings, and the claims are hereby incorporated by reference in theirentirety.

BACKGROUND

The present disclosure relates to video processing systems which performimage processing with respect to a divided image and output theresultant image.

The resolution of video data has been increased to the high definition(HD) resolution, leading to the penetration of Blu-ray discs, thecommencement of digital broadcasting, and the like. This has beenaccompanied by the development of display devices (plasma panels, liquidcrystal panels, projectors, etc.) having higher resolutions.HD-resolution display devices are becoming popular. The resolution aswell as the display screen size of display devices are still increasing.Panels having the 4K×2K resolution which is four times as high as the HDresolution have been developed. It is more than likely that an imageprocessing technique of upconverting HD to 4K×2K will be required inorder to display HD video sources (video data of Blu-ray, digitalbroadcasting, and the like) on display devices having a higherresolution (4K×2K resolution).

In conventional HD processing systems, when images having the 4K×2K sizeare processed, a clock (CLK) frequency may be caused to be four times ashigh in order to improve the processing performance. To achieve this,the microfabrication process and the high-speed transmission interfaceneed to be enhanced, which is not a practical solution.

Therefore, in the conventional art, images having a super resolution(e.g., the 4K×2K resolution) may be processed using a configurationshown in FIG. 11. Note that such a conventional 4K×2K image processingsystem is described in, for example, Japanese Patent Publication No.2007−108447.

In FIG. 11, the system includes four image processors 1105-1108 each ofwhich is capable of processing HD-size images. The system divides inputimage data into four pieces of sub-image data (sub-video), which areprocessed by the image processors 1105-1108. Pseudo-pixel inserters1101-1104 are provided in a preceding stage from the image processors1105-1108. Image trimmers 1109-1112 are provided in a succeeding stagefrom the image processors 1105-1108.

The pseudo-pixel inserters 1101-1104 each perform a process of insertingpseudo-pixels which are calculated from the sub-video into a regionoutside an effective pixel region at a division boundary of the imagedata. Thereafter, the image processors 1105-1108 perform processing. Asa result, the division boundary can be subjected to a spatiallycontinuous process using the pseudo-pixels instead of an end process.The image trimmers 1109-1112 in the succeeding stage remove thepseudo-pixel data regions which have been inserted by the pseudo-pixelinserters 1101-1104 in the preceding stage.

With the aforementioned configuration, a technique of reducing thedisturbance of an image at the division boundary when the sub-images arerecombined has been devised in conventional super-resolution imageprocessing systems.

SUMMARY

However, in the division boundary process of the aforementionedconfiguration, the pseudo-pixels generated from the effective pixelregion are used, and in some pseudo-pixel generating manners, the imagedisturbance occurs at the division boundary after processing by theimage processors in the succeeding stage as in the case wherepseudo-pixels are not generated, which is a problem.

In view of the aforementioned problems, the present disclosure has beenmade. The detailed description describes implementations of a videoprocessing system which divides video data into pieces of sub-video dataand performs image processing with respect to the sub-video data, and inwhich a degradation in an image at a division boundary is reduced orprevented, thereby providing higher image quality.

In the present disclosure, when N image processors each of which iscapable of processing high definition (HD)-size video and is synchronouswith an HD synchronization signal are provided, image processing isperformed with respect to sub-video data of each of a plurality ofsub-regions obtained by dividing the HD-size image while adjacentsub-regions overlap at their boundary.

Specifically, an example video processing system of the presentdisclosure includes N (N is an integer of two or more) image processorseach configured to be capable of processing high definition (HD)-sizevideo and be synchronous with an HD synchronization signal, a regiondivision calculator configured to control data transfer regions of the Nimage processors, and an image processing mode controller configured tocontrol image processing modes of the N image processors. The N imageprocessors process N respective pieces of sub-video data obtained bydividing video data, and the processed N pieces of sub-video data arecombined in a succeeding stage from the N image processors.

In the example video processing system of the present disclosure, eachof the N image processors may include an overlapping region calculatorconfigured to calculate an overlapping region at an image boundarybetween adjacent regions of the N pieces of sub-video data obtained bythe region division calculator, an active period generator configured togenerate an active period of video data based on the result of thecalculation of the overlapping region calculator, a data requestgenerator configured to request data transfer corresponding to theactive period, a resizing processor configured to resize boundary videodata, an image quality improving image quality adjuster configured sothat a mode thereof is set by the image processing mode controller, andan image trimmer configured to remove data of the overlapping region.

Thus, in the present disclosure, the pieces of sub-video data to beprocessed overlap at the image boundary, whereby it is possible toreduce or prevent disturbance which occurs at the image boundary whenimage combination in a succeeding stage is performed at the regionboundary using an end process.

In the example video processing system of the present disclosure, the Nimage processors may perform image processing with respect to theoverlapping region during a blanking period of the HD synchronizationsignal.

Thus, in the present disclosure, image processing is performed withrespect to the overlapping region during the blanking period of the HDsynchronization signal, whereby an increase in the load of imageprocessing corresponding to the overlapping region can be reduced orprevented.

In the example video processing system of the present disclosure, theimage quality improving image quality adjuster may have a mechanismconfigured to store a cumulative value of feature amounts or motiondetection results of video. Cumulative values of the sub-images may beintegrated and judged by the image processing mode controller, and theresult of the judgment may be used to set the mode of the image qualityimproving image quality adjuster again.

Thus, in the present disclosure, the sub-images can be processed in thesame image processing mode.

In the example video processing system of the present disclosure, eachof the N image processors may include a combiner configured to combine aplurality of image planes. The region division calculator may calculatedivision coordinates and size information of combination screens fromscreen combination coordinates, and set the result of the calculationinto the data request generators of the N image processors so thatscreen combination is performed with respect to the N pieces ofsub-video data.

Thus, in the present disclosure, multiple-screen combination, such asPicture in Picture (PIP) and the like, and on-screen display (OSD)superimposition can be achieved.

Another example video processing system of the present disclosureincludes N (N is an integer of two or more) image processors eachconfigured to be capable of processing high definition (HD)-size videoand be synchronous with an HD synchronization signal, and an imageprocessing mode controller configured to control image processing modesof the N image processors. The N image processors process the same videodata. The image processing mode controller sets different imageprocessing modes into the N image processors. N screens are combinedafter image processing of the N image processors.

Thus, in the present disclosure, the same image is processed in Ndifferent image processing modes and the resultant N images are combinedinto a single screen, which is then displayed, whereby the imageprocessing modes can be compared.

Another example video processing system of the present disclosureincludes N (N is an integer of two or more) image processors eachconfigured to be capable of processing high definition (HD)-size videoand be synchronous with an HD synchronization signal. Operating clocksof the N image processors can be separately stopped.

Thus, in the present disclosure, by stopping the operating clocks for(N−1) image processors when HD-size data is output without changing thesize, power consumption can be reduced.

As described above, according to the present disclosure, when N HD-sizeimage processors are used to perform image processing with respect toinput N pieces of sub-image data, and the processed N pieces ofsub-image data are combined into 4K×2K-size image data, it is possibleto reduce or prevent disturbance at the image boundary.

Moreover, according to the present disclosure, in imaging processing forconversion to 4K×2K, the same image is processed in N different imageprocessing modes, and the resultant N images are combined into a singlescreen, whereby the image processing modes can be compared.

Moreover, according to the present disclosure, even when N HD-size imageprocessors are provided to perform image processing for conversion to4K×2K, HD-size data may be output without changing the size. In thiscase, power consumption can be reduced by stopping operating clocks for(N−1) image processors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a video processing system according to afirst embodiment of the present disclosure.

FIG. 2 is a diagram showing a configuration of an image processorincluded in the video processing system of FIG. 1.

FIG. 3 is a diagram showing a process of dividing video data in thevideo processing system of FIG. 1.

FIG. 4 is a timing chart of the image processor of FIG. 2.

FIG. 5 is a diagram showing a video processing system according to asecond embodiment of the present disclosure.

FIG. 6 is a diagram showing a configuration of an image processorincluded in the video processing system of FIG. 5.

FIG. 7 is a diagram showing a process of dividing video data in thevideo processing system of FIG. 5.

FIG. 8 is a diagram showing a video processing system according to athird embodiment of the present disclosure.

FIG. 9 is a diagram showing a configuration of an image processing modecontroller included in the video processing system of FIG. 8.

FIG. 10 is a diagram showing a video processing system according to afourth embodiment of the present disclosure.

FIG. 11 is a diagram showing a conventional video processing system.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described with referenceto the accompanying drawings.

First Embodiment

A first embodiment of the present disclosure will be describedhereinafter with reference to FIGS. 1-4.

FIGS. 1 and 2 are diagrams showing a configuration of a video processingsystem according to the first embodiment of the present disclosure. FIG.3 is a diagram showing the manner in which an image is divided in thefirst embodiment. FIG. 4 is a timing chart of the video processingsystem of the first embodiment of the present disclosure. Firstly, theconfiguration of the video processing system 100 of the first embodimentwhich increases the resolution of high-definition (HD) image data intothe 4K×2K resolution will be described with reference to FIG. 1. In thefirst embodiment, the video processing system 100 includes four imageprocessors 101-104 each of which is capable of processing HD-size videoand is synchronous with an HD synchronization signal, a region divisioncalculator 105 which controls data transfer regions of the four imageprocessors 101-104, and an image processing mode controller 106 whichcontrols image processing modes of the image processors 101-104.

A configuration of each of the image processors 101-104 of the firstembodiment will be described with reference to FIG. 2. The imageprocessors 101-104 each include an overlapping region calculator 112which calculates an overlapping region at a boundary of each adjacenttwo of four sub-images obtained from the region division calculator 105,an active period generator 111 which generates a process active periodof the image processor based on the overlapping regions calculated bythe overlapping region calculator 112, a data request generator 110which requests data transfer corresponding to the active period, aresizing unit (resizing processor) 107 which resizes boundary videodata, an image quality improving image quality adjuster 108 whose modeis set by the image processing mode controller 106, and an image trimmer109 which removes the overlapping region data.

Operation of the video processing system thus configured will bedescribed hereinafter. It is assumed that decoded video data fromdigital broadcasting, an HD-compliant disk, or the like is stored in anexternal memory, such as a dynamic random access memory (DRAM) or thelike. A position of the video data in the external memory is set intothe region division calculator 105. In order to transfer four pieces ofsub-video data to the respective corresponding image processors 101-104,positions of the four pieces of sub-video data are set into therespective corresponding image processors 101-104. In this case, animage having the HD size (1920×1080) is divided into four regions (A, B,C, and D) each having the QHD size (960×540).

The division of an image into four regions will be described withreference to FIG. 3. Here, the upper left region is referred to as aregion A, the upper right region is referred to as a region B, the lowerright region is referred to as a region C, and the lower left region isreferred to as a region D. The transfer start position of each region isdefined as follows: (Xa, Ya)=(0, 0) for the region A, (Xb, Yb)=(960, 0)for the region B, (Xc, Yc)=(960, 540) for the region C, and (Xd, Yd)=(0,540) for the region D. The image processor 101 processes the region A.The image processor 102 processes the region B. The image processor 103processes the region C. The image processor 104 processes the region D.When receiving the division data position, each image processor receivesa data position, and performs calculation using the overlapping regioncalculator 112, taking into consideration overlapping regions (α pixels,β lines) flanking division boundaries, sets a data transfer size and aposition corresponding to the result of the calculation into the datarequest generator 110, and sets an image processing size into theresizing unit 107 and the image quality improving image quality adjuster108. Here, α and β are determined, depending on at least the number oftaps in a process in the horizontal or vertical direction in theresizing unit 107 and the image quality improving image quality adjuster108 of each image processor.

In the case of the image processor 101 for the region A, the divisiondata position (Xa, Ya) and the data transfer size ((960+α) pixels,(540+β) lines) are set into the data request generator 110, the resizingunit 107, and the image quality improving image quality adjuster 108.Similarly, in the case of the image processor 102 for the region B, thedivision data position (Xb−α, Yb) and the data transfer size ((960+α)pixels, (540+β) lines) are set. In the case of the image processor 103for the region C, the division data position (Xc−α, Yc−β) and the datatransfer size ((960+α) pixels, (540+β) lines) are set. In the case ofthe image processor 104 for the region D, the division data position(Xd, Yd−β) and the data transfer size ((960+α) pixels, (540+β) lines)are set.

The active period generator 111 which generates a process active periodof the image processor receives information about the overlapping regionfrom the overlapping region calculator 112 to generate an active periodfor the corresponding image processing region.

FIG. 4 is a timing chart showing a relationship between the processactive periods of the image processors 101-104 and processing lines inthe vertical direction. For the regions A and B are extended so thatlower regions thereof overlap the regions D and C, respectively, by βlines, and the resultant regions A and B are subjected to imageprocessing. In this case, the image processing of the overlapping lowerregions is performed during a lower vertical blanking period of an HDvertical synchronization signal. The regions C and D are extended sothat upper regions thereof overlap the regions B and A, respectively, byβ lines, and the resultant regions C and D are subjected to imageprocessing. In this case, the image processing of the overlapping upperregions is performed during an upper vertical blanking period of the HDvertical synchronization signal. Also in the case of the horizontaldirection, image processing is performed with respect to pixelsincluding overlapping regions in the horizontal direction duringblanking periods of an HD horizontal synchronization signal.

The resizing unit 107 enlarges an image of ((960+α) pixels, (540+β)lines) to an image of (2×(960+α) pixels, 2×(540+β) lines). Thereafter,the image quality improving image quality adjuster 108 whose mode hasbeen set by the image processing mode controller 106 performs imagequality improving image processing with respect to the image containingthe overlapping regions. Thereafter, the image trimmer 109 trims theimage into an image having the HD size (1920×1080). In this case, linesand pixels removed by the trimming are those during vertical andhorizontal blanking periods. Thereafter, the pieces of data of the fourregions having the HD size enlarged by the image processors 101-104 insimilar manners are combined into video having the 4K×2K size after theprocessing of the video processing system. In this case, the boundariesof the four regions are subjected to image processing using theoverlapping regions without performing an end process, i.e., continuousvideo data is used. As a result, disturbance does not occur at theboundaries when the four regions are combined.

The image quality improving image quality adjuster 108 may include amechanism which stores a cumulative value of feature amounts or motiondetection results of video, and an image quality adjusting mechanism(not shown) which determines an image processing mode based on thecumulative value. In this case, the image processing mode controller 106integrates and judges the cumulative values of the four sub-images, andsets a mode in the image quality improving image quality adjusters 108again. As a result, the sub-images can be processed in the same imageprocessing mode. Therefore, it is possible to avoid the situation thatpieces of sub-video are processed in different image processing modesand combined into an unnatural image.

With the aforementioned configuration of the first embodiment, whenvideo data is divided, overlapping regions corresponding to the numberof taps in image processing are processed during blanking periods of HDhorizontal and vertical synchronization signals. As a result, theresizing process and the image quality improving process can beperformed with respect to division boundaries without performing an endprocess. Thereafter, only data corresponding to the active period isoutput. As a result, even when a single piece of video data is dividedinto pieces of sub-video data which are then processed by the separateimage processors 101-104 before being combined, disturbanceadvantageously does not occur at the boundaries.

The image quality improving image quality adjuster 108 has the mechanismwhich stores a cumulative value of feature amounts or motion detectionresults of video. The image processing mode controller 106 integratesand judges the cumulative values of the sub-images, and sets a mode inthe image quality improving image quality adjusters 108 again. As aresult, the sub-images can be processed in the same image processingmode. Therefore, it is possible to avoid the situation that pieces ofsub-video are processed in different image processing modes and combinedinto an unnatural image.

The size of the decoded video data in the external memory in the firstembodiment may be that of an interlaced material (1920×540), the SDsize, or 4K×2K in addition to the HD size (1920×1080).

In the image processors 101-104 of the first embodiment, the order inwhich the resizing unit 107 and the image quality improving imagequality adjuster 108 are arranged on the data path may be reversed.

While, in the first embodiment, video data is divided into four piecesand four image processors are provided, the present disclosure is notlimited to four. The present disclosure may provide a system in whichvideo data is divided into N pieces (N is an integer of two or more) andN image processors are provided.

Second Embodiment

Next, a second embodiment of the present disclosure will be describedwith reference to FIGS. 5-7.

FIGS. 5 and 6 are diagrams showing a configuration of a video processingsystem according to the second embodiment of the present disclosure.FIG. 7 is a diagram showing the manner in which an image is divided inthe second embodiment.

Firstly, the configuration of the video processing system 500 of thesecond embodiment which increases the resolution of video in which imagedata having the standard definition (SD) resolution is displayed inimage data having the high definition (HD) resolution (Picture inPicture (PIP)) to the 4K×2K resolution, will be described with referenceto FIG. 5.

In the second embodiment, the video processing system 500 includes fourimage processors 501-504 each of which is capable of processing HD-sizevideo and is synchronous with an HD synchronization signal, a regiondivision calculator 505 which controls data transfer regions of the fourimage processors 501-504, and an image processing mode controller 506which controls image processing modes of the image processors 501-504.

A configuration of each of the image processors 501-504 of the secondembodiment will be described with reference to FIG. 6. The imageprocessors 501-504 each include an overlapping region calculator 515which calculates an overlapping region at a boundary of each adjacenttwo of four sub-images obtained from the region division calculator 505,an active period generator 514 which generates a process active periodof the image processor based on the overlapping regions calculated bythe overlapping region calculator 515, two data request generators 512and 513 which request data transfer corresponding to the active period,two resizing units 507 and 508 which resize boundary video data, acombiner 509 which can combine a plurality of image planes, an imagequality improving image quality adjuster 510 whose mode is set by theimage processing mode controller 506, and an image trimmer 511 whichremoves the overlapping region data.

Operation of the video processing system thus configured will bedescribed hereinafter. It is assumed that a piece of decoded video datahaving the HD size and a piece of decoded video data having the SD sizefrom digital broadcasting, an HD-compliant disk, or the like are storedin an external memory, such as a dynamic random access memory (DRAM) orthe like. In this case, the video having the SD size is eventuallydisplayed as a PIP, where the base point of the video having the SD sizeis a position (i, j) of the video having the HD size.

The positions of the pieces of video data in the external memory are setinto the region division calculator 505. The division data positions areset into the respective corresponding image processors 501-504 in orderto transfer the four pieces of sub-video data to the respectivecorresponding image processors 501-504. In this case, as shown in FIG.7, the image having the HD size (1920×1080) is divided into four regions(A, B, C, and D) having the QHD size (960×540). Here, the upper leftregion is referred to as a region A, the upper right region is referredto as a region B, the lower right region is referred to as a region C,and the lower left region is referred to as a region D. The transferstart position of each region is defined as follows: (Xa, Ya)=(0, 0) forthe region A, (Xb, Yb)=(960, 0) for the region B, (Xc, Yc)=(960, 540)for the region C, and (Xd, Yd)=(0, 540) for the region D. The imageprocessor 501 processes the region A. The image processor 502 processesthe region B. The image processor 503 processes the region C. The imageprocessor 504 processes the region D.

The manner in which the image having the SD size (720×480) is dividedand transferred to the image processors 501-504 is calculated by theregion division calculator 505 based on a screen combination positionand a combination screen size.

1) When (i, j) is located in the region A, (i+720, j) is located in theregion B, and (i, j+480) is located in the region D, i.e.,((960−720)≦i≦960 and (540−480)≦j≦540), the SD-size image has thefollowing transfer start positions:

(Pa, Qa)=(0, 0)

(Pb, Qb)=(960−i, 0)

(Pc, Qc)=(960−i, 540−j)

(Pd, Qd)=(0, 540−j)

The transfer image sizes are:

(960−i)×(540−j) for SDa

(720−(960−i))×(540−j) for SDb

(720−(960−i))×(480−(540−j)) for SDc

(960−i)×(480−(540−j)) for SDd

The screen combination positions of the sub-screens in the regions A, B,C, and D are:

(ia, ja)=(i, j)

(ib, jb)=(0, j)

(ic, jc)=(0, 0)

(id, jd)=(i, 0)

2) When (i, j) is located in the region A, (i+720, j) is located in theregion A, (i, j+480) is located in the region D, i.e., (i≦(960−720),(540−480)<j<540), the regions B and C are not involved with screencombination. Therefore, SD-size sub-screens corresponding to the imageprocessors 502 and 503 are not transferred. The transfer start positionsof the SD-size sub-screens transferred to the regions A and D are:

(Pa, Qa)=(0, 0)

(Pd, Qd)=(0, 540−j)

The transfer image sizes are:

720×(540−j) for SDa

720×(480−(540−j)) for SDd

The screen combination positions of the sub-screens in the regions A andD are:

(ia, ja)=(i, j)

(id, jd)=(i, 0)

3) When (i, j) is located in the region A, (i+720, j) is located in theregion B, and (i, j+480) is located in the region A, i.e.,((960−720)<i<960 and j≦(540−480)), the regions C and D are not involvedwith screen combination. Therefore, SD-size sub-screens corresponding tothe image processors 503 and 504 are not transferred. The transfer startpositions of the SD-size sub-screens transferred to the regions A and Bare:

(Pa, Qa)=(0, 0)

(Pb, Qb)=(960−i, 0)

The transfer image sizes are:

(960−i)×540 for SDa

(720−(960−i))×540 for SDb

The screen combination positions of the sub-screens in the regions A andB are:

(ia, ja)=(i, j)

(id, jd)=(0, j)

4) When (i, j) is located in the region A, (i+720, j) is located in theregion A, and (i, j+480) is located in the region A, i.e., (i≦(960−720)and j (540−480)), the regions B, C, and D are not involved with screencombination. Therefore, SD-size sub-screens corresponding to the imageprocessors 502, 503, and 504 are not transferred. The transfer startposition of the SD-size sub-screen transferred to the region A is:

(Pa, Qa)=(0, 0)

The transfer image size is:

720×480 for SDa

The screen combination position of a sub-screen in the region A is:

(ia, ja)=(i, j)

5) When (i, j) is located in the region B and (i, j+480) is located inthe region C, i.e., (960≦i, (540−480)<j<540), the regions A and D arenot involved with screen combination. Therefore, SD-size sub-screenscorresponding to the image processors 501 and 504 are not transferred.The transfer start positions of the SD-size sub-screens transferred tothe regions B and C are:

(Pb, Qb)=(0, 0)

(Pc, Qc)=(0, 540−j)

The transfer image sizes are:

720×(540−j) for SDb

720×(480−(540−j)) for SDc

The screen combination positions of the sub-screens in the regions B andC are:

(ib, jb)=(i, j)

(ic, jc)=(i, 0)

6) When (i, j) is located in the region B and (i, j+480) is located inthe region B, i.e., (i≦(960−720), j≦(540−480)), the regions A, C, and Dare not involved with screen combination. Therefore, SD-size sub-screenscorresponding to the image processors 501, 503, and 504 are nottransferred. The transfer start position of the SD-size sub-screentransferred to the region B is:

(Pb, Qb)=(0, 0)

The transfer image size is:

720×480 for SDb

The screen combination position of a sub-screen in the region B is:

(ib, jb)=(i, j)

7) When (i, j) is located in the region D and (i+720, j) is located inthe region C, i.e., ((960−720)<i≦960, 540≦j), the regions A and B arenot involved with screen combination. Therefore, SD-size sub-screenscorresponding to the image processors 501 and 502 are not transferred.The transfer start positions of the SD-size sub-screens transferred tothe regions C and D are:

(Pc, Qc)=(0, 0)

(Pd, Qd)=(960−i, 0)

The transfer image sizes are:

(720−(960−i))×540 for SDc

(960−i)×540 for SDd

The screen combination positions of the sub-screens in the regions C andD are:

(ic, jc)=(0, j)

(id, jd)=(0, 0)

8) When (i, j) is located in the region D and (i+720, j) is located inthe region D, i.e., (i (960−720), 540 j), the regions A, B, and C arenot involved with screen combination. Therefore, SD-size sub-screenscorresponding to the image processors 501, 502, and 503 are nottransferred. The transfer start position of the SD-size sub-screentransferred to the region D is:

(Pd, Qd)=(0, 0)

The transfer image size is:

720×480 for SDd

The screen combination position of a sub-screen in the region D is:

(id, jd)=(i, j)

9) When (i, j) is located in the region C, i.e., (960≦i, 540≦j), theregions A, B, and D are not involved with screen combination. Therefore,SD-size sub-screens corresponding to the image processors 501, 502, and504 are not transferred. The transfer start position of the SD-sizesub-screen transferred to the region C is:

(Pc, Qc)=(0, 0)

The transfer image size is:

720×480 for SDc

The screen combination position of a sub-screen in the region C is:

(ic, jc)=(i, j)

When receiving the division data position, the transfer size, and thescreen combination position of each of the HD-size video and the SD-sizevideo, the image processors 501-504 each perform calculation using theoverlapping region calculator 515, taking into consideration overlappingregions (α pixels, β lines) flanking division boundaries, set a datatransfer size and a position corresponding to the result of thecalculation into the data request generators 512 and 513, and set animage processing size into the resizing units 507 and 508 and the imagequality improving image quality adjuster 510. Here, α and β aredetermined, depending on at least the number of taps in a process in thehorizontal or vertical direction in the resizing units 507 and 508 andthe image quality improving image quality adjuster 510 of each imageprocessor.

The resizing units 507 and 508 enlarge the HD-size sub-video data from((960+α) pixels, (540+β) lines) to (2×(960+α) pixels, 2×(540+β) lines),and also enlarges the SD-size sub-video data from (u pixels, v lines) to(2×(u+α) pixels, 2×(v+β) lines) where (u pixels, v lines) is the size ofeach sub-video data. Thereafter, the combiner 509 performs screencombination based on positions (2 in, 2jn) (n=a, b, c, and d). The imagequality improving image quality adjuster 510 whose mode has been set bythe image processing mode controller 506 performs image qualityimproving image processing with respect to the image containing theoverlapping regions. In this case, lines and pixels removed by thetrimming are those during vertical and horizontal blanking periods.Thereafter, the pieces of data of the four regions having the HD sizeenlarged by the image processors 501-504 in similar manners are combinedinto video having the 4K×2K size after the processing of the videoprocessing system. In this case, the boundaries of the four regions aresubjected to image processing using the overlapping regions withoutperforming an end process, i.e., continuous video data is used. As aresult, the PIP display of HD-size video and SD-size video can beachieved without disturbance occurring at the boundaries when the fourregions are combined.

With the aforementioned configuration of the second embodiment, twopieces of video data are each divided into four pieces by performingcalculation using the region division calculator 505 based on screencombination positions and combination screen sizes, and controllingtransfer of the image processors 501-504, and the two-screen combinationprocess is performed by each of the separate image processors 501-504.Therefore, when the resultant four screens are subsequently combined,disturbance does not occur at the boundaries.

The size of the decoded video data in the external memory in the secondembodiment may be that of an interlaced material (1920×540) or 4K×2K inaddition to the HD size (1920×1080) and the SD size (720×480).

The size of the decoded video data in the external memory in the secondembodiment may be that of on-screen display (OSD) data in addition tothat of video data.

The two-screen combination process of the second embodiment may besuperimposition of on-screen display (OSD) data in addition to Picturein Picture (PIP).

While, in the second embodiment, video data is divided into four piecesand four image processors are provided, the present disclosure is notlimited to four. The present disclosure may provide a system in whichvideo data is divided into N pieces (N is an integer of two or more) andN image processors are provided.

Third Embodiment

A third embodiment of the present disclosure will be describedhereinafter with reference to FIGS. 8 and 9.

FIGS. 8 and 9 are diagrams showing a configuration of a video processingsystem according to the third embodiment of the present disclosure.

The configuration of the video processing system 800 of the thirdembodiment will be described with reference to FIG. 8, in which thehigh-definition (HD) resolution is increased to the 4K×2K resolution,and image quality adjustment can be executed and selected while the usercompares favorite types of image quality adjustment. The videoprocessing system 800 of the third embodiment includes four imageprocessors 801-804 each of which is capable of processing HD-size videoand is synchronous with an HD synchronization signal, and an imageprocessing mode controller 805 which controls image processing modes ofthe image processors 801-804.

FIG. 9 shows a configuration of the image processing mode controller 805of the third embodiment. The image processing mode controller 805includes an image quality adjustment parameter table 806 which holdssetting parameters of image quality adjustment of the image processors801-804, and an image quality adjustment parameter selector 807 whichgenerates an address which is used to extract a set value from theparameter table.

Operation of the video processing system thus configured will bedescribed.

It is assumed that HD-size decoded video data from digital broadcasting,an HD-compliant disk, or the like is stored in an external memory, suchas a dynamic random access memory (DRAM) or the like, four types ofimage quality adjustment are performed with respect to the video data sothat the user selects a favorite image quality adjustment mode, theresultant HD-size images are combined into 4K×2K-size video after theprocessing of the video processing system. Initially, similar datatransfer sizes, positions, and image processing sizes are set into theimage processors 801-804 so that the same decoded HD video data in theexternal memory is transferred to the image processors 801-804.

In the image processing mode controller 805, in the normal mode, theimage quality adjustment parameter selector 807 selects a correspondingaddress from the image quality adjustment parameter table 806, and setsthe same image quality adjustment setting parameter as an imageprocessing mode of the four image processors 801-804. In the thirdembodiment, when a mode in which the user can compare types of imagequality adjustment is set into the image processing mode controller 805,the image quality adjustment parameter selector 807 generates addressesof the image quality adjustment parameter table 806 corresponding tofour image quality adjustment modes to be compared by the user, andselects and extracts four image quality adjustment parameters from theimage quality adjustment parameter table 806. The four image qualityadjustment parameters are set into the respective image processors801-804.

The four image processors 801-804 are controlled so that the same HDimage data are input thereto. In this case, different image qualityadjustment modes are set in the image quality improving image qualityadjusters 108 (FIG. 2) of the four image processors 801-804, andtherefore, the image processors 801-804 performs four types of imageprocessing with respect to the same HD image data and outputs fourpieces of HD image data. After the processing of the video processingsystem, the four pieces of HD-size image data are combined into4K×2K-size video. As a result, the same HD image data is subjected tofour types of image quality improving image quality adjustment, and theresultant four pieces of image data having the 4K×2K size which willconstitute one frame are output.

With the aforementioned configuration of the third embodiment, the sameHD image data is subjected to four types of image quality improvingimage quality adjustment, and the resultant four pieces of image dataare output as a video frame having the 4K×2K resolution. As a result,the user can select a favorite image quality adjustment mode whilecomparing other image quality adjustment modes.

The image quality adjustment parameter table of the third embodiment maynot be provided. Image quality adjustment parameters may be individuallyset.

While, in the third embodiment, video data is divided into four piecesand four image processors are provided, the present disclosure is notlimited to four. The present disclosure may provide a system in whichvideo data is divided into N pieces (N is an integer of two or more) andN image processors are provided.

Fourth Embodiment

A fourth embodiment of the present disclosure will be describedhereinafter with reference to FIG. 10.

FIG. 10 is a diagram showing a configuration of a video processingsystem according to the fourth embodiment of the present disclosure.

The configuration of the video processing system of the fourthembodiment will be described with reference to FIG. 10, which canincrease the high definition (HD) resolution to the 4K×2K resolution,and is connected to a video display device in a succeeding stage whichhas the HD resolution rather than the 4K×2K resolution. The videoprocessing system of the fourth embodiment includes four imageprocessors 1001-1004 each of which is capable of processing HD-sizevideo and is synchronous with an HD synchronization signal, andtwo-input AND circuits 1005-1008 which stop system clocks (operatingclocks) with which the image processors 1001-1004 are separatelyoperated. The AND circuits 1005-1008 each receive the correspondingsystem clock and a system clock gating signal dedicated to thecorresponding image processor.

Operation of the video processing system thus configured will bedescribed hereinafter.

It is assumed that HD-size decoded video data from digital broadcasting,an HD-compliant disk, or the like is stored in an external memory, suchas a dynamic random access memory (DRAM) or the like, the videoprocessing system increases the resolution of the video data to the4K×2K resolution and outputs the video data having the 4K×2K resolution,and a video display device in a succeeding stage which is connected tothe video processing system has the HD display resolution.

The image processors 1001-1004 which process HD-size images normallydivides HD-size video data into four pieces of sub-video data andenlarge the sub-video data in order to output 4K×2K size video data,i.e., upconverts the HD video data into 4K×2K video data. However, whenthe video display device in the succeeding stage which is connected tovideo processing system has only the HD display resolution (e.g., thevideo display device is connected via an HDMI cable), the videoprocessing system can recognize the maximum resolution of the videodisplay device.

The video processing system, when recognizing that a video displaydevice having the HD display resolution is connected to itself, stopsthe system clocks for three of the four image processors 1001-1004 usingseparate system clock gating signals. As a result, the 4K×2K videoprocessing system can reduce power consumption to that for an HD systemwhen outputting HD-size video.

With the aforementioned configuration of the fourth embodiment, when anHD-size video display device is connected to the 4K×2K video processingsystem, the 4K×2K video processing system can stop system clocks whichare used to operate three of the four image processors 1001-1004 forprocessing 4K×2K images. As a result, the 4K×2K video processing systemcan reduce power consumption to that for an HD system when outputtingHD-size video.

As described above, the present disclosure can process boundaries ofsub-images without a degradation in image quality and is thereforeuseful for video processing systems.

1. A video processing system comprising: N (N is an integer of two ormore) image processors each configured to be capable of processing highdefinition (HD)-size video and be synchronous with an HD synchronizationsignal; a region division calculator configured to control data transferregions of the N image processors; and an image processing modecontroller configured to control image processing modes of the N imageprocessors, wherein the N image processors process N respective piecesof sub-video data obtained by dividing video data, and the processed Npieces of sub-video data are combined in a succeeding stage from the Nimage processors.
 2. The video processing system of claim 1, whereineach of the N image processors includes an overlapping region calculatorconfigured to calculate an overlapping region at an image boundarybetween adjacent regions of the N pieces of sub-video data obtained bythe region division calculator, an active period generator configured togenerate an active period of video data based on the result of thecalculation of the overlapping region calculator, a data requestgenerator configured to request data transfer corresponding to theactive period, a resizing processor configured to resize boundary videodata, an image quality improving image quality adjuster configured sothat a mode thereof is set by the image processing mode controller, andan image trimmer configured to remove data of the overlapping region. 3.The video processing system of claim 2, wherein the N image processorsperform image processing with respect to the overlapping region during ablanking period of the HD synchronization signal.
 4. The videoprocessing system of claim 3, wherein the image quality improving imagequality adjuster has a mechanism configured to store a cumulative valueof feature amounts or motion detection results of video, and cumulativevalues of the sub-images are integrated and judged by the imageprocessing mode controller, and the result of the judgment is used toset the mode of the image quality improving image quality adjusteragain.
 5. The video processing system of claim 3, wherein each of the Nimage processors includes a combiner configured to combine a pluralityof image planes, and the region division calculator calculates divisioncoordinates and size information of combination screens from screencombination coordinates, and sets the result of the calculation into thedata request generators of the N image processors so that screencombination is performed with respect to the N pieces of sub-video data.6. A video processing system comprising: N (N is an integer of two ormore) image processors each configured to be capable of processing highdefinition (HD)-size video and be synchronous with an HD synchronizationsignal; and an image processing mode controller configured to controlimage processing modes of the N image processors, wherein the N imageprocessors process the same video data, the image processing modecontroller sets different image processing modes into the N imageprocessors, and N screens are combined after image processing of the Nimage processors.
 7. A video processing system comprising: N (N is aninteger of two or more) image processors each configured to be capableof processing high definition (HD)-size video and be synchronous with anHD synchronization signal, wherein operating clocks of the N imageprocessors can be separately stopped.